Photosensor

ABSTRACT

For a photosensor, an array substrate is provided, wherein the edge of a photodiode is enclosed by the opening edge of a contact hole formed on a drain electrode.

This application claims priority from Japanese Patent Application No.2007-127889 filed on May 14, 2007, the entire subject matter of which isincorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a flat-panel photosensor that includesan active matrix type TFT array substrate, on which a photodiode forconverting visible light into electric charges and a thin-filmtransistor (hereinafter referred to as a TFT) employed as a switchingelement are arranged like a matrix.

2. Description of the Related Art

A flat-panel photosensor that includes a TFT array substrate, on which aphotodiode for performing photoelectric conversion of visible light anda TFT are arranged, is applied as a contact image sensor or an X-rayimage display apparatus, and is widely employed. Especially, aflat-panel X-ray image display apparatus (hereinafter referred to as anFPD), which is constituted by providing, on a TFT array substrate, ascintillator that converts X rays into visible light, is a favorableapparatus for the application to, for example, a medical industry.

In the X-ray image diagnosis field, observation of a detailed image(still image) and observation of a real-time image (moving picture) areperformed for different purposes. An X-ray film is still employed mainlyto obtain a still picture, while an image pickup tube (imageintensifier) that includes a photomultiplier and a CCD is employed toobtain a moving picture. The X-ray film provides a high spatialresolution, but there are several drawbacks: the X-ray film has a lowsensitivity and enables radiographing of only still pictures, and sincethe developing process is required after radiographing, this is notappropriate for instantaneous use. On the other hand, the image pickuptube provides a high sensitivity and enables radiographing of a movingpicture. However, the image pickup tube has a low spatial resolution,and since this is a vacuum device, the increase of the device size islimited.

For an FPD, there are an indirect conversion type that converts X raysinto light using a scintillator, such as CsI, and then converts thelight into electric charges using a photodiode, and a direct conversiontype that directly converts X rays into electric charges using an X-raydetection element, such as Se. The indirect conversion type provideshigh quantum efficiency and a superior signal/noise ratio, and requiresonly a small amount of exposure to perform X-ray radiographing and imagepickup. The structure of the array substrate of the indirect conversiontype FPD and the manufacturing method thereof have been disclosed (see,for example, JP-A-2004-63660 (FIG. 9), JP-A-2004-48000 (FIG. 4) andJP-A-2003-158253 (FIG. 1)).

Formation of a photodiode that influences the sensitivity of aphotosensor and noise is important for the array substrate of an FPD. Aphotosensor includes amorphous silicon layers deposited on an electrode.For example, as in JP-A-2004-63660, when a photosensor is formed on acathode electrode that includes the same layer as the gate electrode ofa thin film transistor, the following problem has risen. Specifically,when a lower electrode 609 of a photodiode is formed of the samematerial as used for a gate electrode layer, the electrode 609 receivesmore damage caused by dry etching, or caused by forming a sourceelectrode layer 605 and a drain electrode layer 606, because theelectrode 609 is located at the lowermost as well as the gate electrodelayer. Accordingly, surface roughness occurs and a leak current from thephotodiode is increased. In order to avoid this problem, for example,high-melting-point metal must be employed to form the lower electrode609 of the photodiode. In this case, an aluminum alloy film having a lowresistance can not be employed to form a gate electrode and gate wiring.Further, a margin of an opening size will be reduced for connectionbetween the source electrode layer 605 and the cathode electrode layer609. In order to avoid this problem, as disclosed in JP-A-2004-48000 orJP-A-2003-158253, the lower electrode for a photosensor might be formedon an electrode that is formed of the same layer as the source electrodeand the drain electrode of a thin film transistor.

One of the methods for improving the output performance of thephotosensor is a method for increasing the ratio of the dimension of anSi layer, which serves as an photodiode, to the dimension of one sensorcomponent. Therefore, in a conventional structure described in, forexample, JP-A-2004-48000 or JP-A-2003-158253, a photodiode encloses acontact hole that is a diode bottom contact opening. That is, the Silayer that constitutes a photodiode is formed to cross the edge of acontact hole. However, in this structure, it is found through ourevaluation that, when the opening edge length obtained by adding thelengths of edges, i.e., the circumferential length of the opening of thecontact hole was increased, the current leak element was increased. Asthis reason, we consider that, when a step difference formed by acontact hole is present in a formation area for an Si layer thatconstitutes a photodiode, the Si layer unevenly grows at the stepdifference, or a membrane stress is generated in the Si layer at thestep difference. Since the increase of a leak current deteriorates thesensitivity of a photosensor, inhibition of a leak current isindispensable.

SUMMARY OF THE INVENTION

A flat-panel photosensor according to this invention includes a TFTarray substrate wherein a step difference does not exist in an areawhere a photodiode formed of Si layers is located above a drainelectrode.

A margin for an opening size for connection between a source electrodeand a gate electrode need not be considered, and a step differenceformed by a contact hole is eliminated in a formation area for Silayers, which constitute a photodiode provided for a photosensor. Thus,an uneven growth of an Si layer at the step difference can be prevented,and the occurrence of a membrane stress at the step difference can beprevented. As a result, a homogeneous Si layer is obtained for aphotodiode, and a leak current of a photosensor can be inhibited.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a TFT array substrate provided for aphotosensor according to a first embodiment of the preset invention;

FIG. 2 is a cross-sectional view of the TFT array substrate provided forthe photosensor according to the first embodiment;

FIG. 3 is a cross-sectional view of a terminal portion according to thefirst embodiment;

FIG. 4 is a cross-sectional view of a terminal portion according to thefirst embodiment;

FIGS. 5A to 5C are cross-sectional views of the TFT array substrateprovided for the photosensor according to the first embodiment;

FIGS. 6A and 6B are cross-sectional views of the TFT array substrateprovided for the photosensor according to the first embodiment;

FIG. 7 is a plan view of a TFT array substrate in a different examplefor the first embodiment;

FIG. 8 is a cross-sectional view of the TFT array substrate in thedifferent example for the first embodiment;

FIG. 9 is a plan view of a TFT array substrate provided for aphotosensor according to a second embodiment of the preset invention;

FIG. 10 is a cross-sectional view of the TFT array substrate providedfor the photosensor according to the second embodiment;

FIG. 11 is a plan view of a TFT array substrate provided for aphotosensor according to a third embodiment of the preset invention;

FIG. 12 is a cross-sectional view of the TFT array substrate providedfor the photosensor according to the third embodiment;

FIG. 13 is a plan view of a TFT array substrate provided for aphotosensor according to a fourth embodiment of the preset invention;

FIG. 14 is a cross-sectional view of the TFT array substrate providedfor the photosensor according to the fourth embodiment;

FIG. 15 is a plan view of a TFT array substrate provided for aphotosensor in a different example for the fourth embodiment;

FIG. 16 is a cross-sectional view of the TFT array substrate providedfor the photosensor in the different example for the fourth embodiment;

FIG. 17 is a plan view of a TFT array substrate provided for aphotosensor according to a fifth embodiment of the preset invention;

FIG. 18 is a cross-sectional view of the TFT array substrate providedfor the photosensor according to the fifth embodiment;

FIG. 19 is a plan view showing a general configuration of the TFT arraysubstrate according to the invention; and

FIG. 20 shows a general configuration of an X-ray image pickup apparatusaccording to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

The preferred embodiments of the present invention will be specificallydescribed while referring to drawings. FIG. 1 is a plan view of a TFTarray substrate 200 provided for a photosensor according to a firstembodiment of this invention. FIG. 2 is a cross-sectional view of aportion indicated by A-A in FIG. 1.

A gate electrode 2 is made of metal that contains aluminum as theprimary element, and is formed on a glass substrate 1 that is aninsulating substrate. As metal that contains aluminum as the primaryelement, an Al alloy that contains Ni, such as AlNiNd, AlNiSi or AlNiMg,i.e., an Al—Ni alloy is employed. However, another aluminum alloy may beemployed, or instead of Al, Cu may be employed as a low electricalresistant metal material. Further, the gate electrode 2 may be providedby laminating metal films. A gate insulating film 3 is deposited tocover the gate electrode 2, and a semiconductor layer 4 is formedopposite the gate electrode 2. An n+a-Si:H ohmic contact layer 5 isformed on the semiconductor layer 4, and a source electrode 6 and adrain electrode 7 are arranged to be connected to the semiconductorlayer 4 via the ohmic contact layer 5. In addition, a first passivationfilm 8 is formed to cover these components.

A P (Phosphorus)-doped amorphous silicon film 9, an intrinsic amorphoussilicon film 10 and a B (Boron)-doped amorphous silicon film 11 arelaminated in the named order so as to obtain a photodiode 100 having athree-layer structure that is to be connected to the drain electrode 7via a contact hole CH1 that is open through the first passivation film8. The photodiode 100 functions as an example of the photosensor. Thatis, numeral 100 also denotes the photosensor. Incidentally, aphototransistor, a photo IC and a phototube, etc., can be used as thephotosensor. On the photodiode 100, a transparent electrode 12 made ofIZO, ITZO or ITSO is formed. This embodiment has a feature that theopening of the contact hole CH1 is shaped so as to enclose thephotodiode 100. That is, the photodiode 100 is formed inside the openingedge of the contact hole CH1, so that the photodiode 100 does not crossthe opening edge of the contact hole CH1. Further, the photodiode 100 isalso enclosed inside the pattern for the drain electrode 7. That is, alower layer of the photodiode 100 is substantially flat. In other words,a step difference is not present in an area where the photodiode 100 isformed. Therefore, since a portion that crosses the opening edge of thecontact hole CH1 or the step difference formed by the drain electrode 7is not present in the amorphous silicon layer lamination of thephotodiode 100, a satisfactory photodiode where little current leakageoccurs can be obtained. Here, the opening edge indicates a stripedportion, around the opening of the contact hole CH1, substantially in asquare shown in FIG. 1. When the contact hole CH1 is tapered, theopening edge indicates especially the bottom portion. Furthermore, forthe sake of convenience, the portion of the drain electrode 7 that islocated between the area on the semiconductor layer 4 and the area toform the photodiode 100 and that couples these areas may be called aconnection portion 7 a.

A second passivation film 13 having contact holes CH2 and CH3 isdeposited to cover the above described structure. A data line 14 on thesecond passivation film 13 is connected to the source electrode 6 viathe contact hole CH2, and a bias line 15 on the second passivation film13 is connected via the contact hole CH3 to the transparent electrode12. An Al—Ni alloy film is applied at least to the topmost layers or thelowermost layers of the data line 14 and the bias line 15. Only a singlelayer of an Al—Ni alloy film may be applied for the data line 14 and thebias line 15. When an Al—Ni alloy film is employed as the topmost layer,a nitride layer may be additionally deposited on the surface.Furthermore, although not shown, the data line 14 is used as wiring toread an electric charge obtained through conversion by the photodiode100 that has a three-layer structure. The bias line 15 is wiring used toapply a reverse bias to the photodiode 100, so that the photodiode 100is set to the OFF state when it is not exposed to light. A lightblocking layer 16 is also formed on the second passivation film 13. Athird passivation film 17 and a fourth passivation film 18 are depositedto cover the above described components. The fourth passivation film 18is a film having a flat surface, and is made of, for example, an organicresin.

Terminal portions will now be described while referring to FIGS. 3 and4. FIG. 3 is a cross-sectional view of a terminal portion formed at theend of gate wiring that is extended from the gate electrode 2. FIG. 4 isa cross-sectional view of a terminal portion formed at the end of wiringthat is extended from the data line 14 or the bias line 15.

Referring to FIG. 3, a gate wiring end portion 20 is formed on the glasssubstrate 1, at the same time as the gate electrode 2 is formed. Thegate insulating film 3, the first passivation film 8 and the secondpassivation film 13 are laminated on the gate wiring end portion 20, andon the lamination, a conductive pattern 21 is overlaid at the same timeas the data line 14 is formed. The conductive pattern 21 is connectedvia a contact hole CH4 to the gate wiring end portion 20. The contacthole CH4 may be formed in the same etching process as for the contactholes CH2 and CH3. Further, since the contact hole CH4 is formed in atapered shape, step coverage of the conductive pattern 21 is increased,and a wire break can be prevented.

Furthermore, a third passivation film 17 and a fourth passivation film18 are deposited on the conductive pattern 21, and a terminal leadelectrode 22 is formed on the third passivation film 17 and the fourthpassivation film 18. The terminal lead electrode 22 and the conductivepattern 21 are connected together via a contact hole CH5 that is openthrough the third passivation film 17 and the fourth passivation film18. In this embodiment, the terminal lead electrode 22 is made of atransparent conductive oxide; however, a film lamination where ahigh-melting-point metal film is deposited as a lower layer may beemployed.

Referring to FIG. 4, short ring wiring 23 is formed on the glasssubstrate 1 at the same time as the gate electrode 2 is formed. The gateinsulating film 3, the first passivation film 8 and the secondpassivation film 13 are laminated on the short ring wiring 23, and awiring end portion 24, extended from the data line 14 or the data line15, is arranged on the lamination. The wiring end portion 24 isconnected to the short ring wiring 23 via a contact hole CH6. Thecontact hole CH6 may be formed in the same etching process as for thecontact holes CH2 and CH3. When the contact hole CH6 is formed in atapered shape, step coverage of the wiring end portion 24 can beincreased, and a wire break can be prevented.

In addition, the third passivation film 17 and the fourth passivationfilm 18 are deposited on the wiring end portion 24, and the terminallead electrode 22 is formed on the third passivation film 17 and thefourth passivation film 18. The terminal lead electrode 22 and thewiring end portion 24 are connected together via a contact hole CH7 thatis open through the third passivation film 17 and the fourth passivationfilm 18. It should be noted that the terminal lead electrode 22 may alsobe a lamination of an upper layer of a transparent conductive oxide anda lower layer of a high-melting-point metal.

Using a TFT array substrate 200 shown in FIGS. 1 and 2, a photosensor,such as an X-ray image pickup apparatus as shown in FIG. 20, can also bemanufactured by a well known method. Although not shown, for productionof an X-ray image pickup apparatus, a scintillator, such as a CsI, thatconverts X rays into visible light is formed on the fourth passivationfilm 18 in FIG. 1 by performing vapor deposition. Then, a digital boardon which a low noise amplifier and an A/D converter are mounted, adriver board that drives a TFT and a reading board that reads electriccharges are connected to the photosensor as shown in FIG. 19. In thismanner, an X-ray image pickup apparatus can be prepared.

In the TFT array substrate provided for the photosensor of thisembodiment, a step difference formed by a contact hole can be eliminatedin the formation area for Si layers that constitute a photodiode.Therefore, an uneven growth of the Si film at the step difference isremoved, and a membrane stress at the step difference can be prevented.Thus, a homogenous Si layer that constitutes a photodiode is obtained,and a leak current can be inhibited. Further, for the TFT arraysubstrate provided for the photosensor of this embodiment, when thesource electrode and the drain electrode of the thin film transistor andthe lower electrode for a photodiode are to be formed, a pattern for thesame layer as the gate wiring is not exposed. Thus, a low electricalresistant metal alloy, such as aluminum or copper, can be employed toform gate wiring, and a large photosensor can be produced.

A method for manufacturing the TFT array substrate provided for thephotosensor of this embodiment will now be described while referring toFIGS. 5A to 5C and FIGS. 6A and 6B. FIGS. 5 and 6 are cross-sectionalviews of the portion shown in FIG. 2 at the individual steps of themanufacturing processing.

First, the first conductive thin film is deposited on the glasssubstrate 1, by sputtering, using metal that employs aluminum as theprimary element, e.g., an Al alloy, such as AlNiNd, that contains Ni.The film deposition condition is pressure of 0.2 to 0.5 Pa, DC power of1.0 to 2.5 kW or a power density of 0.17 to 0.43 W/cm² and a filmdeposition temperature ranging from a room temperature to about 180° C.The film thickness is 150 to 300 nm. Further, in order to prevent areaction to a developer, an AlNiNdN layer may be deposited on the AlNiNdlayer. Instead of AlNiNd, AlNiSi or AlNiMg may be employed. And the samematerial may be employed also for the data line 14 and the bias line 15,and in this case, the production efficiency will be increased. Inaddition to Al, Cu or a Cu alloy can be employed as a low electricalresistant metal material, and as well as for Al, the sputtering methodcan be employed. These metal films may also be laminated.

Sequentially, at the first photolithography step, a resist in a gateelectrode shape is formed, and at the etching step, the first conductivethin film is patterned using a mixture of, for example, phosphoric acid,nitric acid and acetic acid to obtain the gate electrode 2. When thecross section of the gate electrode 2 is tapered, the occurrence of adefect, such as a wire break, can be reduced in the succeeding filmdeposition process. In this embodiment, the mixture of phosphoric acid,nitric acid and acetic acid is employed for etching; however, an etchantis not limited to this type, and dry etching may also be performed.According to the structure of this embodiment, since the gate electrode2 is not exposed during the photodiode formation process, even a metalthat contains, as the primary element, aluminum or copper that is lessdurable to a damage can be employed as the gate electrode 2. Therefore,since low electrical resistant wiring can be formed, a large photosensorcan be obtained.

Following this, the gate insulating film 3 of 200 to 400 nm thick, thea-Si: H (amorphous silicon with a hydrogen atom being added)semiconductor layer 4 of 100 to 200 nm thick and the n+a-Si:H ohmiccontact layer 5 of 20 to 50 nm thick are laminated by a plasma CVDmethod. Since high efficiency for reading an electric charge and atransistor that exhibits a high drive performance are required for thephotosensor, the a-Si: H semiconductor layer 4 may be formed in twoprocesses in order to increase the performance of the transistor. As thefilm deposition condition in this case, a low deposition rate of 50 to200 [Å]/minute is employed to form the first high-quality layer, and thedeposition rate of 300 [Å]/minute or higher is employed for the otherfollowing layers. In addition, the deposition temperature of 250 to 350°C. is employed to form the gate insulating film 3, the a-Si:H (amorphoussilicon with a hydrogen atom being added) semiconductor layer 4 and then+a-Si:H ohmic contact layer 5.

Next, at the second photolithography step, a resist in a channel shapeis formed, and at the etching step, the semiconductor layer 4 and theohmic contact layer 5 are patterned with an island shape so as tomaintain a portion that forms a channel. In this process, plasma etchingis performed using, for example, a gas mixture of SF₆ and HCl. When thecross section of a channel is tapered, the occurrence of a defect, suchas a wire break, can be reduced in the succeeding film formationprocess. In this embodiment, a gas mixture of SF₆ and HCl is employed asan etching gas; however, the type of gas is not limited to this.

Thereafter, deposition of the second conductive thin film is performed.In this process, a high-melting-point metal film, such as Cr, isdeposited using, for example, the sputtering method. The film thicknessis 50 to 300 nm.

Sequentially, at the third photolithography step, a resist (not shown)corresponding to a source electrode and a drain electrode is formed, andat the etching step, the second conductive thin film is patterned using,for example, a mixture of cerium ammonium nitrate and nitric acid, andthe source electrode 6 and the drain electrode 7 are obtained.Thereafter, the ohmic contact layer 5 is etched using these electrodes 6and 7 as masks and by plasma that employs a gas mixture of, for example,SF₆ and HCl. As a result, a thin film transistor (TFT) is formed.

Three masks have been employed up to this process. However, at thesecond and third photolithography steps for forming a silicon island andfor forming the source electrode 6, the drain electrode 7 and the ohmiccontact layer 5, a method for employing only one gray tone mask toperform the processing may be employed. Further, a mixture of ceriumammonium nitrate and nitric acid has been employed as an etchant to formthe source electrode 6 and the drain electrode 7, and a gas mixture ofSF₆ and HCl has been used as an etching gas for the ohmic contact layer5. However, gases to be employed are not limited to these examples.Furthermore, in this embodiment, Cr has been employed; however, insteadof Cr, other metal that can obtain an ohmic contact with Si can beemployed. The cross section in this state is shown in FIG. 5A. Forimproving the characteristic of the thin film transistor (TFT), prior toformation of the passivation film 8, the plasma treatment using ahydrogen gas may be performed for this structure so as to roughen theback channel side, i.e., the surface of the semiconductor layer 4.

Following this, the first passivation film 8 is formed by a method, suchas plasma CVD, and at the fourth photolithography step, the contact holeCH1 is formed using a resist (not shown) in order to obtain a contactbetween the drain electrode 7 and the P-doped amorphous silicon film 9.In this process, the first passivation film 8 is patterned throughplasma etching using a gas mixture of, for example, CF₄ and O₂. Thecross section in this state is shown in FIG. 5B.

As the first passivation film 8, a silicon oxide (SiO₂) film having alow permittivity is formed with a thickness of 200 to 400 nm. The filmdeposition condition of a silicon oxide film is an SiH₄ flow rate of 10to 50 sccm, an N₂O flow rate of 200 to 500 sccm, a film depositionpressure of 50 Pa, RF power of 50 to 200 W or a power density of 0.015to 0.67 W/cm², and a film deposition temperature of 200 to 300° C. Inthis embodiment, a gas mixture of CF₄ and O₂ is employed; however, anetching gas is not limited to this. Further, silicon oxide is employedfor the first passivation film 8; however, a material is not limited tothis, and SiN or SiON may be employed. In this case, hydrogen, nitrogenor NH₃ is added to the above described etching gas to form the firstpassivation film 8. At the fourth photolithography step, the openingedge of the contact hole CH1 is formed using a mask that is locatedoutside the edge of an area where the drain electrode 7 and thephotodiode 100 are connected together.

By using the plasma CVD method, the P-doped amorphous silicon film 9,the intrinsic amorphous silicon film 10 and the B-doped amorphoussilicon film 11, which constitute the photodiode 100, are laminated inthe named order in the same deposition chamber, while the vacuum stateis maintained. Of the obtained silicon film lamination, the P-dopedamorphous silicon film 9 is 30 to 80 nm thick, the intrinsic amorphoussilicon film 10 is 0.5 to 2.0 μm thick and the B-doped amorphous siliconfilm 11 is 30 to 80 nm thick. As the deposition condition of theintrinsic amorphous silicon film 10, for example, the SiH₄ flow rate is100 to 200 sccm, the H₂ flow rate is 100 to 300 sccm, the filmdeposition pressure is 100 to 300 Pa, the RF power is 30 to 150 W or thepower density is 0.01 to 0.05 W/cm², and the film deposition temperatureis 200 to 300° C. For depositing the P-doped or B-doped silicon film 9or 11, a gas obtained by mixing 0.2 to 1.0% of PH₃ or B₂H₆ with the gasthat conforms the above described deposition condition is employed.

The B-doped amorphous silicon film 11 may be formed by implanting B tothe upper portion of the intrinsic amorphous silicon film 10 using theion shower doping method or the ion implantation method. When the ionimplantation method is employed to form the B-doped amorphous siliconfilm 11, an SiO₂ film of 5 to 40 nm may be formed in advance on thesurface of the intrinsic amorphous silicon film 10. This is because adamage due to implantation of B is reduced. In this case, after ion isimplanted, the SiO₂ film may be removed using, for example, BHF.

Next, an amorphous transparent conductive film is deposited, bysputtering, using one of targets, IZO, ITZO and ITSO. The filmdeposition condition is 0.3 to 0.6 Pa, DC power of 3 to 10 kW or a powerdensity of 0.65 to 2.3 W/cm², an Ar flow rate of 50 to 150 sccm, anoxygen flow rate of 1 to 2 sccm and a film deposition temperatureranging from a room temperature to about 180° C. After the amorphoustransparent conductive film has been formed, at the fifthphotolithography step, a resist (not shown) is formed and is etchedusing oxalic acid to perform patterning, and the transparent electrode12 is obtained. The cross section in this state is shown in FIG. 5C.

Oxalic acid has been employed for etching; however, an etchant is notlimited to this. In this embodiment, since a film that contains eitherIZO, ITZO or ITSO is employed as the transparent electrode 12, the filmdeposition process can be performed under an amorphous state in whichtiny crystal grains are almost not included in the underneath B-dopedamorphous silicon film 11. Therefore, this method provides effects thatlittle etch residue remains. Further, a film that contains a mixture ofthe above described materials may be employed as the transparentelectrode 12, or films formed of the individual materials or filmsformed of a mixture of these materials may be laminated.

Sequentially, at the sixth photolithography step, a resist pattern isformed so as to be a little larger than the pattern of the transparentelectrode 12 and to be located inside the opening edge of the contacthole CH1. Then, the three amorphous silicon layers, i.e., the P-dopedamorphous silicon film 9, the intrinsic amorphous silicon film 10 andthe B-doped amorphous silicon film 11 are patterned using plasma of agas mixture of, for example, SF₆ and HCl. The gas mixture of SF₆ and HClhas been employed for etching; however, an etching gas is not limited tothis. As a result, the photodiode 100 having a three-layer structure isobtained. The cross section in this state is shown in FIG. 6A.

The photodiode 100 that includes three layers, i.e., the P-dopedamorphous silicon film 9, the intrinsic amorphous silicon film 10 andthe B-doped amorphous silicon film 11, and is arranged inside theopening edge of the contact hole CH1. Therefore, the photodiode 100 islocated also inside the pattern end for the drain electrode 7. Accordingto this arrangement, since the photodiode 100 does not cross the openingedge of the contact hole CH1 or the pattern end of the drain electrode7, the increase of a leak current due to a step difference can beinhibited. That is, an uneven growth of the Si film at the stepdifference can be eliminated, and the occurrence of a membrane stressdue to the step difference can be prevented. Further, the Si layers thatconstitute the photodiode become homogenous, and the increase of a leakcurrent due to the step difference at the opening edge can be inhibited.

Next, the second passivation film 13 for protecting the photodiode 100is formed, and at the seventh photolithography step, a resist pattern(not shown) is formed in correspondence with the contact hole CH2, viawhich the source electrode 6 connects to the data line 14, and thecontact hole CH3, via which the transparent electrode 12 of thephotodiode 100 connects to the bias line 15. Thereafter, the resist ispatterned with the contact holes CH2 and CH3 using plasma of a gasmixture of CF₄ and Ar. At this time, the contact hole CH4 that connectsthe gate wiring end portion 20 to the conductive pattern 21 and thecontact hole CH6 may also be formed.

As the second passivation film 13, a silicon oxide film having a lowpermittivity is deposited with a thickness of 0.5 to 1.5 μm in order toreduce a load capacitance imposed on the data line 14 and the bias line15. The film deposition condition for the silicon oxide film is an SiH₄flow rate of 10 to 50 sccm, an N₂O flow rate of 200 to 500 sccm, a filmdeposition pressure of 50 Pa, RF power of 50 to 200 W or a power densityof 0.015 to 0.67 W/cm² and a film deposition temperature of 200 to 300°C. Silicon oxide has been employed as the material for the secondpassivation film 13; however, the material is not limited to this, andSiN, for example, may be employed. When the contact holes are formed soas to have a tapered shape in cross section, step coverage of the upperlayer is increased and the occurrence of a wire break, for example, canbe reduced.

Furthermore, in this embodiment, the manufacturing method for formingthe second passivation film 13 and then opening the contact holes CH2and CH3 has been described. However, the manufacturing method is notlimited to this. For example, at the same time as the contact hole CH1is formed, openings may be formed in advance at positions correspondingto the contact hole CH2 and the contact holes CH4 and CH6. In this case,since the first passivation film 8 is not required, the etching periodrequired for forming the openings after the second passivation film 13has been deposited can be reduced.

Following this, the third conductive thin film is deposited in order toobtain the data line 14, the bias line 15 and the light blocking layer16. For the third conductive thin film, an Al alloy containing Ni, suchas AlNiNd, that has a low resistance and a superior heat resistance andexhibits a superior contact property relative to a transparentconductive thin film is employed, and is formed with a thickness of 0.5to 1.5 μm. The data line 14 and the bias line 15 may be provided as asingle AlNiNd layer, a lamination of AlNiNd and Mo or an Mo alloy, or alamination of AlNiNd and a high-melting-point metal, such as Cr.Further, in order to prevent a reaction against a developer, an AlNiNdNfilm may be deposited on the AlNiNd film. In this case, by sputtering,an Mo alloy is formed as an underlayer and AlNiNd is overlaid. The filmdeposition condition is pressure of 0.2 to 0.5 Pa, DC power of 1.0 to2.5 kW or a power density of 0.17 to 0.43 W/cm² and a film depositiontemperature ranging from a room temperature to about 180° C.

At the eighth photolithography step, a resist is formed incorrespondence with the data line 14, the bias line 15 and the lightblocking layer 16, and when the resist is made of an AlNiNd and Molaminated film, patterning is performed using a mixture of, for example,phosphoric acid, nitric acid and acetic acid. The cross section in thisstate is shown in FIG. 6B. In this embodiment, the mixture of phosphoricacid, nitric acid and acetic acid is employed for etching; however, anetchant is not limited to this type. The data line 14 is connected viathe contact hole CH2 to the source electrode 6, and the bias line 15 isconnected via the contact hole CH3 to the transparent electrode 12.Since, as previously described, an Al alloy containing Ni or ahigh-melting-point metal is employed as the lowermost layer of the biasline 15, the contact resistance relative to the lower transparentelectrode 12 is low, and a satisfactory connection can be obtained.

Next, the third passivation film 17 and the fourth passivation film 18are deposited to protect the data line 14 and the bias line 15. In thisembodiment, for example, SiN is employed for the third passivation film17, and a planarization film is employed as the fourth passivation film18.

At the ninth photolithography step, the contact holes CH5 and CH7 toconnect terminals are formed using a resist, and patterning is performedusing plasma of a gas mixture of CF₄ and O₂. In this embodiment, a gasmixture of CF₄ and O₂ is employed for etching; however, an etching gasis not limited to this. It should be noted that, when a photosensitiveplanarization film is employed as the fourth passivation film 18, anexposure and developing process may be performed to pattern the fourthpassivation film 18 at the ninth photolithography step.

Following this, a transparent conductive film that serves as theterminal lead electrode 22 is formed. An electrode material, such asamorphous ITO, is employed in order to obtain reliability. Then, at thetenth photolithography step, a resist in a terminal shape is formed, andis etched using, for example, oxalic acid to obtain the terminal leadelectrode 22. Thereafter, ITO is crystallized by annealing. At thistime, as shown in FIGS. 3 and 4, the terminal lead electrode 22 isconnected via the contact holes CH5 and CH7 to the conductive pattern 21and the wiring end portion 24.

In this embodiment, as shown in FIG. 1 and FIG. 5B, the opening edge ofthe contact hole CH1 is enclosed by the pattern end of the drainelectrode 7. However, this positional relation may be reversed. The planview and the cross-sectional view of a TFT array substrate 200 having areverse arrangement are shown in FIGS. 7 and 8. FIG. 8 is across-sectional view of the portion indicated by A-A in FIG. 7.

Referring to FIGS. 7 and 8, the drain electrode 7 is enclosed by theopening edge of the contact hole CH1. In this case as well as in theabove example, the photodiode 100 that includes the P-doped amorphoussilicon film 9, the intrinsic amorphous silicon film 10 and the B-dopedamorphous silicon film 11 is arranged so as not to cross the stepdifference at the contact hole CH1 or the drain electrode 7. Therefore,the effects of the present invention can also be obtained. Since themanufacturing method is almost the same as the contents described above,except for the size of a mask used when the contact hole CH1 is formed,no further explanation for this will be given. It is preferable,however, that the etching process for opening the contact hole CH1 beperformed under an etching condition that provides etch selectivity forthe gate insulating film 3 located underneath.

Second Embodiment

In the first embodiment, depending on an etching condition, there is acase wherein, in the processing for forming the contact hole CH1 thatconnects the drain electrode 7, which serves as the lower electrode forthe photodiode 100, to the amorphous silicon film 9, a polymer may begenerated by the element of an etching gas and be attached again to thedrain electrode 7. In this state, when the P-doped amorphous siliconfilm 9, the intrinsic amorphous silicon film 10 and the B-dopedamorphous silicon film 11 are deposited to constitute the photodiode100, the adhesion to the drain electrode 7 is deteriorated and theamorphous silicon film might peel off.

According to a second embodiment of the present invention, a leakcurrent of a photodiode 100 is inhibited, and an amorphous silicon filmis prevented from peeling off. This embodiment will now be describedwhile referring to FIGS. 9 and 10. FIG. 9 is a plan view of a TFT arraysubstrate 200 provided for a photosensor for the second embodiment. FIG.10 is a cross-sectional view of a portion indicated by A-A in FIG. 9. InFIG. 9, a contact hole CH1 is indicated by a broken line so as toclearly identify.

As apparent from FIGS. 9 and 10, the feature of the second embodiment isthat a lower electrode 25 for the photodiode 100 is formed to cover thecontact hole CH1 and the photodiode 100 is overlaid so as to beconnected to the lower electrode 25. That is, the photodiode 100 isconnected via the lower electrode 25 to a drain electrode 7. Further, asthe other feature, the photodiode 100 is located near the opening edgeof the contact hole CH1 so as not to cross a portion where the lowerelectrode 25 covers a passivation film 8 (a portion 26 indicated by abroken line in FIG. 10). Therefore, as well as in the first embodiment,since laminated amorphous silicon layers that constitute the photodiode100 do not include a portion that crosses the step difference, thesatisfactory photodiode 100 having little current leakage can beobtained.

A manufacturing method will now be described. Since the same method asin the first embodiment is employed until the contact hole CH1 is formedat the fourth photolithography step, no further explanation for thiswill be given. In the second embodiment, after the contact hole CH1 hasbeen formed, deposition of the fourth conductive thin film that becomesthe lower electrode 25 for the photodiode 100 is performed. In thisprocess, a high-melting-point metal, such as Cr, is deposited by, forexample, sputtering.

Sequentially, at the photolithography step, the lower electrode 25 forthe photodiode 100 is formed to cover the contact hole CH1, and then, aP-doped amorphous silicon film 9, an intrinsic amorphous silicon film 10and a B-doped amorphous silicon film 11 are deposited. Since the lowerelectrode 25 is formed after the contact hole CH1 was open, and sincesurface contamination is rarely left over on the lower electrode 25 andsatisfactory adhesion to the amorphous silicon film lamination isobtained, the films can be prevented from peeling off. There is a casewherein polymer remains at the interface of the drain electrode 7 andthe lower electrode 25 because of an etching gas, and contaminates theinterface. However, relative to a contact resistance to the photodiode100, the increase of a resistance of the contact between the drainelectrode 7 and the lower electrode 25 is so little that a problem doesnot occur.

Since the manufacturing method performed after the amorphous siliconfilm lamination has been formed is the same as in the first embodiment,no further explanation for this will be described. As previouslydescribed, the feature of the second embodiment is that the photodiode100 is located near the opening edge of the contact hole CH1 so as notto cross the portion where the lower electrode 25 covers the passivationfilm 8 (the portion 26 indicated by a broken line in FIG. 10).Therefore, as well as in the first embodiment, since laminated amorphoussilicon layers that constitute the photodiode 100 do not include aportion that crosses the step difference, the satisfactory photodiode100 having little current leakage can be obtained. In addition, when thelower electrode 25 is formed and the photodiode 100 is overlaid, peelingoff of amorphous silicon films, which is caused by polymer that isattached during the process for opening the contact hole CH1, can beprevented.

Third Embodiment

In the second embodiment, the lower electrode 25 has been formed so thatthe pattern end completely covers the contact hole CH1. This is becauseof the following background. Assuming that the lower electrode 25 issmaller than the contact hole CH1, the drain electrode 7 underneath willbe exposed by etching the lower electrode 25. In a case wherein thedrain electrode 7 does not have etch selectivity relative to the lowerelectrode 25, the drain electrode 7 underneath would also be etched.Especially when the connection portion 7 a of the drain electrode 7 isetched, a wire break will occur between the thin film transistor (TFT)and the photodiode 100. Therefore, etch selectivity relative to thedrain electrode 7 is required for the material of the lower electrode25, and the selection range of materials is narrowed. To avoid thisproblem, generally, the lower electrode 25 is formed larger than thecontact hole CH1. That is, the lower electrode 25 is formed to cover thecontact hole CH1.

When the lower electrode 25 is formed too large, however, the lowerelectrode 25 is located too close to the data line 14 and thecapacitance between the wiring is increased. In order to reduce theinter-wiring capacitance, a small lower electrode 25 is preferable.Accordingly, the dimension of the photodiode 100 should be reduced;however, this is difficult, because the reduction of the dimension ofthe photodiode 100 lowers the sensitivity of the photosensor. Therefore,under these circumstances, the lower electrode 25 is arranged as closeas possible to the opening edge of the contact hole CH1. When alignmentoffset of the patterns has occurred, the pattern end of the lowerelectrode 25 might enter inside of the contact hole CH1. In this case,the above described problem on selection of the material for the lowerelectrode 25 also occurs. A third embodiment of this invention resolvesthis problem.

A plan view and a cross-sectional view of a TFT array substrate 200 forthe third embodiment are shown in FIGS. 11 and 12. FIG. 12 is across-sectional view of a portion indicated by A-A in FIG. 11. Referringto FIG. 12, in addition to the portion 26 in the second embodiment, aportion 27 is also shown as an area, near the opening edge of thecontact hole CH1, where the lower electrode 25 covers the passivationfilm 8. The feature of the third embodiment is that a distance of theportion 26 where the lower electrode 25 overlaps the passivation film 8,i.e., an overlap distance W1, is greater than an overlap distance W2 ofthe portion 27 where the lower electrode 25 overlaps the passivationfilm 8.

As shown in FIG. 11, the portion 26 is an area corresponding to theconnection portion 7 a where a TFT and the photodiode 100 are connectedtogether. Therefore, a relationship of the overlap distances in FIG. 12can be rephrased as follows. In the third embodiment, the TFT arraysubstrate 200 is formed, so that the overlap distance W1 for theconnection portion 7 a is greater than the overlap distance W2 for thearea other than the connection portion 7 a. Thus, the increase of thecapacitance imposed on the data line 14 can be minimized, and when adefect, such as alignment offset, has occurred during the manufacturingprocessing, a wire break is rarely caused at the connection portion 7 a.These effects are increased especially when the same material isemployed for the lower electrode 25 and the drain electrode 7 to improvethe productivity, or when only an electrode material having aninappropriate etch selectivity is available to be employed. The methodfor manufacturing the TFT array substrate 200 of the third embodiment isthe same as the method of the second embodiment, except for a maskpattern used at the step of patterning the lower electrode 25 and thecontact hole CH1. Therefore, no further explanation for this will begiven.

Further, in the third embodiment, the photodiode 100 includes a P-dopedamorphous silicon film 9, an intrinsic amorphous silicon film 10 and aB-doped amorphous silicon film 11, and is arranged so as not to cross astep difference formed by the contact hole CH1, the drain electrode 7 orthe lower electrode 25. Therefore, the effects provided by the firstembodiment can also be obtained. In addition, as well as in the secondembodiment, the bond lift-off of the P-doped amorphous silicon film 9,the intrinsic amorphous silicon film 10 and the B-doped amorphoussilicon film 11 can be prevented.

Fourth Embodiment

In the third embodiment, an overlap portion has been increased at theconnection portion 7 a, compared with the portion other than theconnection portion 7 a in order to prevent a wire break that may becaused at the connection portion 7 a at the occurrence of an alignmenterror. A difference of a fourth embodiment from the third embodiment isthat an area other than the connection portion 7 a includes a portionwhere the pattern end of a lower electrode 25 is positioned inside acontact hole CH1. With this arrangement, a capacitance imposed on a dataline 14 can be more reduced.

A plan view and a cross-sectional view of a TFT array substrate 200according to the forth embodiment are shown in FIGS. 13 and 14. FIG. 14is a cross-sectional view of a portion indicated by A-A in FIG. 13.Referring to FIG. 13, in the whole area other than the connectionportion 7 a, the pattern end of the lower electrode 25 is positionedinside the contact hole CH1. However, the arrangement is not limited tothis.

That is, in an area other than the connection portion 7 a, thepositional relation of the contact hole CH1 and the lower electrode 25may be locally reversed, and both a portion where the lower electrode 25and a passivation film 8 overlap and a portion where these components donot overlap may be present. For example, only in a portion near thewiring, such as the data line 14, the pattern end of the lower electrode25 may be positioned inside the contact hole CH1. A manufacturing methodfor the fourth embodiment is the same as for the second embodiment,except for a mask pattern used at the step for patterning the lowerelectrode 25 and the contact hole CH1, and no further explanation forthis will be given. As previously described, since a drain electrode 7is exposed during the process for etching the lower electrode 25, it ispreferable that a material that has etch selectivity relative to thedrain electrode 7 be employed for the lower electrode 25.

Furthermore, the opening edge of the contact hole CH1 is enclosed by thepattern end of the drain electrode 7. However, this positionalrelationship may be reversed. A plan view and a cross sectional view ofa TFT array substrate 200 with a reversed arrangement are shown in FIGS.15 and 16. FIG. 16 is a cross-sectional view of a portion indicated byA-A in FIG. 15. In FIG. 15, the drain electrode 7 is enclosed by theopening edge of the contact hole CH1, and the lower electrode 25 isarranged to have the same size as the drain electrode 7, or to enclosethe drain electrode 7. Also in this case, a photodiode 100 that includesa P-doped amorphous silicon film 9, an intrinsic amorphous silicon film10 and a B-doped amorphous silicon film 11 is formed so as not to crossa step difference formed by the contact hole CH1, the drain electrode 7or the lower electrode 25. Therefore, the effects of the invention canbe obtained. Further, bond lift-off of the P-doped amorphous siliconfilm 9, the intrinsic amorphous silicon film 10 and the B-dopedamorphous silicon film 11 can be prevented. Since the manufacturingmethod is almost the same as that described above, except for the sizeof a mask used to open the contact hole CH1, no further explanation forit will be given. It is preferable, however, that the etching processfor opening the contact hole CH1 be performed under an etching conditionproviding etch selectivity for the gate insulating film 3 locatedunderneath.

Fifth Embodiment

In the first embodiment, the photodiode 100 is enclosed by the openingedge of the contact hole CH1 and the drain electrode 7 in order toprovide the photodiode 100 having little current leakage. In the secondto fourth embodiments, the photodiode 100 is enclosed by the lowerelectrode 25 on the assumption that the photodiode 100 is arrangedinside the opening edge of the contact hole CH1. However, thesearrangements of the photodiode 100 must be designed by considering, atleast, at the photolithography step, two alignment margins, i.e., analignment margin between the contact hole CH1 and the drain electrode 7and an alignment margin between the contact hole CH1 and the photodiode100, and the final uniformity of three components, i.e., the contacthole CH1, the drain electrode 7 and the photodiode 100. Therefore, thereis a case wherein the dimension of the photodiode 100 is reduced and theopen area ratio is lowered.

According to a fifth embodiment of the invention, a leak current of aphotodiode 100 can be inhibited, and peeling off of amorphous siliconfilms can be prevented without reducing an open area ratio. Thisembodiment will now be described while referring to FIGS. 17 and 18.FIG. 17 is a plan view of a TFT array substrate 200 provided for aphotosensor according to this embodiment. FIG. 18 is a cross-sectionalview of a portion indicated by A-A in FIG. 17.

A manufacturing method for the fifth embodiment is the same as thesecond embodiment, except for a process for forming a drain electrode 7,the position where a contact hole CH1 is open and the size of a maskused to form a lower electrode 25. Thus, no further explanation for themethod will be given. Referring to FIG. 17, the feature of the fifthembodiment is that the contact hole CH1 that connects the drainelectrode 7 to the lower electrode 25 does not enclose amorphous siliconfilm lamination that serves as a photodiode 100, and is formed at aposition different from that of the photodiode 100. Further, since theamorphous silicon film lamination that serves as the photodiode 100 isarranged so as to be enclosed by the lower electrode 25, and since thereis not an area that crosses a step difference formed by the drainelectrode 7, the contact hole CH1 or the lower electrode 25, thephotodiode 100 having little current leakage can be provided. With thisarrangement, at the photolithography step for the photodiode 100, onlyan alignment margin between the photodiode 100 and the lower electrode25 is required. Therefore, the alignment margin is reduced compared withthat in the first or second embodiment, and the open area ratio can beincreased. Further, since the amorphous silicon films are laminated onthe lower electrode 25, peeling off of the amorphous silicon films canbe prevented.

A TFT of reverse stagger channel etch type that employs amorphoussilicon has been employed for this embodiment. However, a polysiliconTFT or an MOS using crystal silicon may also be employed. Or, a devicehaving a switching function and a photodiode may be employed together.

An array substrate obtained by the above method can be employed toproduce a photosensor, such as X-ray image pickup apparatus as shown inFIG. 20, using a well known method. Although not shown, a scintillator,such as a CsI, that converts X rays into visible light is formed, byvapor deposition, on or above the fourth passivation film 18 in FIG. 2,and a digital board, on which a low noise amplifier and an A/D converterare mounted, a driver board that drives a TFT and a reading board thatreads electric charges are connected to the photosensor as shown in FIG.19. In this manner, an X-ray image pickup apparatus can be prepared.

1. A photosensor comprising: a TFT array substrate of active matrixtype, on which a photodiode and a thin film transistor are arranged likea matrix, wherein the thin film transistor comprises: a plurality ofgate wiring lines each having a gate electrode; a semiconductor layerprovided for the gate electrode via a gate insulating film; and a sourceelectrode and a drain electrode connected to the semiconductor layer,wherein the TFT array substrate comprises: a passivation film depositedon the thin film transistor, the source electrode and the drainelectrode; a contact hole opened through the passivation film; and aphotodiode connected via the contact hole to the drain electrode, andwherein the photodiode is arranged inside an opening edge of the contacthole and inside a pattern for the drain electrode, and wherein a lowerlayer of the photodiode is substantially flat.
 2. The photosensoraccording to claim 1, further comprising: a lower electrode formed so asto be connected to the drain electrode via the contact hole, wherein thephotodiode is arranged so as to be connected via the lower electrode tothe drain electrode.
 3. The photosensor according to claim 2, whereinthe lower electrode is formed to cover the opening edge of the contacthole.
 4. The photosensor according to claim 2, wherein the drainelectrode includes a connection portion that is located between an areaon the semiconductor layer and an area where the photodiode is formedand that connects those two areas, and wherein an overlap distance ofthe connection portion where the lower electrode covers the contact holeis greater than an overlap distance of a portion, other than theconnection portion, where the lower electrode covers the contact hole.5. The photosensor according to claim 2, wherein the drain electrodeincludes a connection portion that is located between an area on asemiconductor layer and an area where the photodiode is formed and thatconnects those two areas; and wherein a portion other than theconnection portion includes a portion where the lower electrode ispositioned inside the opening edge of the contact hole.
 6. Thephotosensor according to claim 1, wherein a step difference is notpresent in an area where the photodiode is formed.
 7. The photosensoraccording to claim 1, wherein metal used to form the gate electrodecontains metal that employs aluminum or copper as the primary element.8. The photosensor according to claim 7, wherein the metal that employsaluminum as the primary element is either AlNiNd, AlNiSi or AlNiMg. 9.The photosensor according to claim 1, wherein a scintillator is formedabove the passivation film, and wherein at least a digital board onwhich a low noise amplifier and an A/D converter are mounted, a driverboard that drives the thin film transistor and a reading board thatreads an electric charge are connected to the photosensor.
 10. Thephotosensor according to claim 9, wherein the scintillator converts Xrays into visible light to provide a function for displaying an X rayimage.
 11. A photosensor comprising: a TFT array substrate of activematrix type, on which a photodiode and a thin film transistor arearranged like a matrix, wherein the thin film transistor includes aplurality of gate wiring lines each having a gate electrode, asemiconductor layer provided for the gate electrode via a gateinsulating film, and a source electrode and a drain electrode connectedto the semiconductor layer, wherein the TFT array substrate includes apassivation film deposited on the thin film transistor, the sourceelectrode and the drain electrode, a contact hole opened through thepassivation film, a lower electrode formed so as to be connected via thecontact hole to the drain electrode, and a photodiode formed so as to beconnected via the lower electrode to the drain electrode, and whereinthe contact hole is formed at a position different from that of thephotodiode.
 12. The photosensor according to claim 11, wherein metalused to form the gate electrode contains metal that employs aluminum orcopper as the primary element.
 13. The photosensor according to claim12, wherein the metal that employs aluminum as the primary element iseither AlNiNd, AlNiSi or AlNiMg.
 14. The photosensor according to claim11, wherein a scintillator is formed above the passivation film, andwherein at least a digital board on which a low noise amplifier and anA/D converter are mounted, a driver board that drives the thin filmtransistor and a reading board that reads an electric charge areconnected to the photosensor.
 15. The photosensor according to claim 14,wherein the scintillator converts X rays into visible light to provide afunction for displaying an X ray image.